We’re introducing a new blogger to the site: Dr. Fred A. Engleberry. Dr. F.A.E. holds a PhD from MIT (Muckton Institute of Talknology) and has several months of valuable experience with applied technology. We are pleased to have Dr. F.A.E. available to answer questions collected from customers around the world.
Dr. F.A.E, “Smoky” from General Specifics Inc. sent a question…”Why did my FET fail?” Without further ado, we’ll turn the session over to Dr. Fred.
First of all, Smoky, you’re probably expecting a lot of annoying questions about your design. Such as, what frequency you’re running at, what the gate drive circuit looks like, what the load is and what supply voltage is present. Some design engineers might try to determine whether there is an avalanche condition beyond what the device might be reasonably expected to tolerate, whether the gate drive is insufficient or oscillating, whether the load is inductive, whether voltage spikes creep too close to breakdown voltages on the gate or drain, or whether the total package dissipation is being exceeded.
However, let’s say in this instance I could see your schematic and Bill of Materials (BOM). Your gate resistor, R42, as noted on the schematic, should be one ohm, but the BOM shows 1,000 ohms. Replace this resistor with the proper value and you will find that your FET turn-on and turn-off rise and fall times will become reasonable and you will avoid gate oscillation – and your FET design will become robust.
Want more information on FETs? Check out our website for MOSFETs at http://fairchildsemi.com/products/mosfets/index.html
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Dear Dr. FAE,
In my experience the gate drive resistor is sometimes raised to a higher value to help pass compliance tests. The rise and fall times I am sure are now much faster but this can also lead to much higher radiated emsisons from hitting the FET with a sharper slew rate.
Is there a trade off or a better way to control this problem?
Thanks!
Hello Glen. Often a small resistor is used to slow down the turn-on and turn-off times and thus limit excitation of the parasitic resonances and reduce ringing (EMI), but 1000 ohms would be way too large. I’ve seen as much as 100 ohms used, but I think that’s too large. I’m glad Dr. Engleberry is sleeping in right now because he’d give you a differential equation to solve just to punish you. The best solution is a great layout to minimize parasitics, then a snubber. Of course, as FET manufacturers, we’ll always recommend something that makes the FET run as cool as possible. Slowing down the turn-on and turn-off makes the FET run in the linear region longer and increases switching losses.
Dr. Engleberry left out another cause that I have experienced…ESD wounded parts. Althout this is not as common today as it was in the old days; a good ESD zap can seem to have no effect on the operation of a FET but can eventually lead to premature infarction of the gate insulator. Also, regarding slowing down the gate charging rate to reduce EMC, this is of course a second choice to reducing the drain-source circuit current loop area. But, if you are like most engineers in large companies, you are often commanded to fix the problem without changing anything, so sometimes a band-aid is called for to get that good review score and move to another group as quickly as possible.