Comments on: Why did my FET fail?

By: Craig Ranta

Craig Ranta — Thu, 27 Aug 2009 20:51:04 +0000

Dr. Engleberry left out another cause that I have experienced…ESD wounded parts. Althout this is not as common today as it was in the old days; a good ESD zap can seem to have no effect on the operation of a FET but can eventually lead to premature infarction of the gate insulator. Also, regarding slowing down the gate charging rate to reduce EMC, this is of course a second choice to reducing the drain-source circuit current loop area. But, if you are like most engineers in large companies, you are often commanded to fix the problem without changing anything, so sometimes a band-aid is called for to get that good review score and move to another group as quickly as possible.

By: Ken Coffman

Ken Coffman — Wed, 26 Aug 2009 20:51:22 +0000

Hello Glen. Often a small resistor is used to slow down the turn-on and turn-off times and thus limit excitation of the parasitic resonances and reduce ringing (EMI), but 1000 ohms would be way too large. I’ve seen as much as 100 ohms used, but I think that’s too large. I’m glad Dr. Engleberry is sleeping in right now because he’d give you a differential equation to solve just to punish you. The best solution is a great layout to minimize parasitics, then a snubber. Of course, as FET manufacturers, we’ll always recommend something that makes the FET run as cool as possible. Slowing down the turn-on and turn-off makes the FET run in the linear region longer and increases switching losses.

By: Glen Tennison

Glen Tennison — Wed, 26 Aug 2009 16:36:58 +0000

Dear Dr. FAE,
In my experience the gate drive resistor is sometimes raised to a higher value to help pass compliance tests. The rise and fall times I am sure are now much faster but this can also lead to much higher radiated emsisons from hitting the FET with a sharper slew rate.
Is there a trade off or a better way to control this problem?
Thanks!