The Joys of Superposition – Part One

September 29, 2011

Dear Dr. Engleberry, I have to analyze the control loop of a circuit that uses your voltage-mode FAN1577A switching regulator, but the complex equations are overwhelming. I like the part with its built-in FET drivers, but the equations? Not so much.

Anxious in Allentown

Dear Anxious. One thing to keep in mind is that the equations are a tool for describing circuit operation and often the circuit value you must derive can be generated with a much less complex formula scribbled on a napkin, pre-digested in a spreadsheet or from a computer model created by someone else. The fact is, there are many ways to understand circuit operation and, as long as the final design meets the requirements, it does not matter which path was taken.

If it is any consolation, some of the great pioneers of electronics felt inadequate when looking at the mathematical representations. Take Michael Faraday for example. He was much more comfortable measuring and documenting the results of his experiments. He was very uncomfortable with the folks who came later and described physics with formulas. After all what is a formula? It does not define nature. The formula is a mental tool which should help us understand the underlying linkages between cause and effect, but no formula is perfect and if it doesn’t shed light? Then throw it out!

One ray of hope I can offer is superposition. Superposition tells us that the behavior of a circuit can be described by analyzing all the individual signals in isolation, then summing the results all together. We don’t have to choke down the whole circuit all at once…we can chop it up into as many pieces as we like and ingest them one-by-one.

However, I don’t want to mislead you. The complexity can still be overwhelming. Let’s start Part 1 of our superposition exercise with the output capacitor you might find in a power supply output.

Courtesy of our friends at Nippon Chemi-Con, I grabbed an 820uF capacitor off my bench. The device says 820uF, so am I safe to use that value in my transfer function? I plugged one into my LCR meter and here’s what I see:

Frequency   Capacitance   ESR

100Khz         -428uF            6.95mOhm

10Khz            745uF            9.5mOhms

1Khz              774uF           12.9mOhm

100Hz           788uF            33mOhm

The datasheet says this is a 820uF, 7 mOhm capacitor with plus and minus 20% initial tolerance. -428uF? What does that mean? It means this component is not a capacitor at 100Khz-its an inductor–and the crossover point (self-resonant frequency where C=L) is somewhere between 10Khz and 100Khz.

So, what do I conclude from this? Via superposition, it’s okay to analyze the operation of this capacitor all on its own…then sum it into the larger circuit. But, if you want to accurately understand the bigger picture, you have to take into account the actual component properties with the signals and conditions it will actually see in your circuit.

We will continue this discussion in The Joys of Superposition, Part 2.

Can we have a brief moment of silence to honor Jim Williams and Bob Pease? The loss of these two giants of the analog design world is immense. We have no choice…though we can’t begin to fill their shoes…we must carry on.

RIP, Jim and Bob.

References:

FAN1577 A http://www.fairchildsemi.com/pf/FA/FAN1577A.html

The Electric Life of Michael Faraday, Alan Hirshfeld, Walker & Company, 2006

Tags: Dr. FAE, Fairchild Semiconductor, switching regulator

How do you stabilize an unruly boost converter?

March 25, 2011

Dear Fred. Can I call you Fred? I hope so. Can you help me? I am trying to stabilize a boost converter, but it reminds me of my three-year-old daughter. She won’t behave. Neither will my boost regulator. I know you like design details. My converter is running with a 100Khz clock. Vin is 12V and Vout is 60V. The output current rating is 100mA. I’m using a 10uH inductor.

PS: My daughter is named Fred too. I named her after you. I am your biggest fan.

Unruly in Redmond

Dear Unruly. I prefer to be addressed as Dr. Engleberry. I ask everyone, even my dear mother who turns 104 next month, to call me Dr. Engleberry. She stubbornly refuses, though I have reminded her 1753 times (yes, I keep track of this sort of thing). You can only imagine how aggravating that is. It steams my cappuccino.

With regard to your boost converter…these designs can be tricky, particularly when the inductor current is continuous and the duty cycle is greater than 50%. Let’s take a look and see where you are.

The clock period is 10µSec.  can be calculated with the following formula:

 Where:   

This gives:    

As I feared, we are running into a problem called the RHP Zero. RHP stands for Right-Half Plane. This sounds complex, but the idea is simple enough. The inductor is ‘charged’ for 8µSec and discharged for 2µSec. As long as the load is stable, everything runs fine, but let’s imagine a fast increase in load current is demanded. The only way to get more power out of the inductor is to put more into it. How do we put more in? With a longer on-period, of course. But, with a fixed-frequency converter, the larger on-period comes at the expense of the off period. With a shorter off-period, we get less output power.

That’s right. We want more output power, but until we establish a new operating point for the inductor, we get less output power. This problem is characteristic of the boost converter and with these operating conditions, there is nothing we can do. The real problem comes when we try to compensate this power supply. If we have too fast of a responses time, then the converter will try to compensate for the reduced output voltage and we’ll see horrible overshoot and undershoot and even worse, instability in the control loop. So, we must roll off the response loop at a much lower frequency than we’d like to see.

What can we do? Abandon the boost converter topology and use a flyback converter?

PS: This is an odd coincidence, but my mother’s name is Fred too.

=========================

You can read more about boost converters in these technical articles:

Building Variable Output Voltage Boost PFC Converters with the FAN9612 Interleaved BCM PFC Controller.

UniFET^TM - Optimized Switch for Discontinuous Current Mode Power Factor Correction.

Specific products related to this are:

FAN5333A   

FAN5340

FAN9612

Tags: boost converter, Dr. FAE, Fairchild Semiconductor, PFC Controller

Adventures in Optocoupling

February 24, 2011

Dear Dr. FAE. You’re always going on and on (and on) about how smart you are…perhaps you’d like a challenge where I give you the answer-and you have to figure out the question. Here’s the answer: a 1150 ohm resistor. You don’t feel so smart now, do you, Dr. Smartypants?

• - Throwing Down in Tampa

Through the application of only a small portion of my intellect, I can tell your question relates to selecting the right pull-up resistor to use for a cost-effective, low-performance optocoupler circuit…to be specific, the half-pitch, mini-flat packaged HMHA281 device. This is a simple circuit, but there are still a few things to consider when designing a reliable and robust detection circuit.

First of all, we need to select a current-limiting resistor for the emitter circuit. With a 12Vin, a forward voltage drop of 1.3V across the LED and a reasonable current of 8mA, let’s figure out what value of resistor should be used…

The closest standard value is 1.33K, so we’ll use that.

We’re using a standard CMOS logic gate (with hysteresis) as a detector on the secondary side. The question is, with the optocoupler turned on, what voltage do we need to provide to make sure the gate input detects a logic zero? So, we look at the NC7SZ14 datasheet. In order to be recognized as a logic zero over a wide operating temperature range, the input voltage must be less than 1.30V.

How do we guarantee a voltage no greater than 1.30V when the detector transistor is on? We’re running this device in a switch mode, so we need to know the minimum Current Transfer Ratio (CTR) with a saturated detector transistor. This is not something that can be read directly off the datasheet but we can derive it from the V_CE(SAT) transfer characteristic in the HMHA281 datasheet. With an I_F of 8mA, we get an I_C of 2.4mA; that gives us a CTR of 2.4/8 or 30%. This is a typical minimum at room temperature, so we need to derate it for temperature. By studying Figure 4 of the HMHA281 datasheet, we see that we need about an 80% derating at 55°C, so that gives us a minimum CTR of about 24%.

Being clever and highly experienced, we know that a gently-treated optocoupler’s CTR will degrade by about 1% per year. If we expect this design to work for ten years, then we should derate the CTR an additional 10%…to 21.6%.

By gently-treated, we mean the optocoupler is not exposed to high ambient temperatures, large emitter/detector currents or extreme thermal cycling. With more aggressive environments and usage, we can expect degradation closer to 2% per year.

With 8mA emitted, then the minimum current in the output phototransistor is:

So, what pull-up resistor value do we need to make sure the voltage at the inverter input is less than 1.30V when 1.73mA flows through it?

We’ll choose 1150 ohms as the closest standard value. Pardon me while I do a little victory waltz. 1150 ohms. Boom, I have dispensed with your challenge.

I don’t anticipate any problems, but we should make sure the ‘off’ current will be detected as a logic ‘one’. According to Figure 8 of the HMHA281 datasheet, we can expect 10uA of dark current at 55°C. This will drop 11.6mV across the pull-up resistor. The resulting voltage at the gate input is much more than 2.2V required to assure a logic ‘one’ is detected. So, all is well.

This was a lot of work to create a low-speed logic interface. If you want us to the hard work, you can use a device with the logic detection built in, like the FODM8061.

There - that is the question to your answer - and yes I do feel smart!

 Let me throw a challenge back at you, TDiT…and to my readers around the world. Here’s the answer: Valvular Conduit. What is the question?

The first right answer in the comment section below will win a trendy and fashionable prize package, including my attractive and collectable signed photograph and a 2N7002 transistor.

 Sincerely, Dr. FAE aka “Smartypants”

Tags: Dr. FAE, Fairchild Semiconductor, FODM8061, HMHA281, NC7SZ14

Gate Charge and On Resistance—I’ll take Less of Both, Please

December 21, 2010

Dear Dr. FAE. It would be really great if you would provide MOSFETs with lower on resistance. Resistance causes heat and this heat represents wasted energy. Why do you hate the environment?

• - Angry in Augusta

Dear Dr. Fred. I am switching your FETs at a high frequency and the switching loss is the dominant loss factor. I don’t understand why you don’t work harder in making parts that switch with less of a gate charge requirement and thus, less wasted energy. Why do you hate the environment and waste so much power?

• - Irked in Indianapolis

Dear Angry and Irked. To your great fortune, the barista made me a most-lovely double-latte with an elaborate heart drawn in the perfect centimeter of creamy foam. Therefore, I vow not to allow anything to aggravate me today. My day will be blissful. Bad traffic on the commute? No problem. Slow pedestrians in the crosswalk? Does not bother me. Annoying questions from the public? I laugh.

We often get questions like this. And really, are there any more unappreciated than the hard-working geniuses who labor in the labs and fabs to give you better MOSFETs year-after-year? We recently announced our first sub-milliohm 30V N-channel (FDMS7650) MOSFET in the Power56 package, and you can believe the sparkling apple juice flowed freely in our engineering departments when this part was released.

So, here’s the deal my friends. You think you’re buying one MOSFET, but the reality is-you’re buying many, perhaps millions. Perhaps many millions. That’s how we reduce the on resistance: by cramming more and more parallel transistors on the die. Our figure of merit is resistance per square centimeter of die area and we attack and reduce this number every year.

Figure 1 Internal FET Construction

I know what you’re thinking…with all of these transistors built with trench technology to maximize the drain and source surface areas, it must be a real challenge to keep the capacitance low to minimize gate charge requirements. Yes, that is a challenge. Here’s the basic equation for capacitance:

Figure 2 Emath, Fundamental Capacitance Calculation

This formula reminds us that capacitance increases with “plate” area and when the distance between the plates is reduced. What this means: as we push resistance lower by adding parallel transistors, the capacitance will generally increase. Of course, we do what we can…note the K (dielectric constant)…we’d benefit if that number could be reduced. Also, we’d benefit if pi was increased, hence our appeal to international standards bodies to increase pi to a bigger, easier-to-remember number like 5 (that’s what we call sophisticated engineering humor, friends).

We deliver value to the market in two ways, we either give you the same on resistance with a smaller die at a lower cost or you get lower on resistance at the same price. How often do people call us up and thank us for this? You’re right, not very often.

We’re conscious of the gate charge requirement and do everything we can to control it (via charge balance) and make it small. As the letters above illustrate, it’s tough to please all customers, but we’ll keep trying.

In answer to the latter questions-as a child I had a beautiful Turkish Angora cat named Emir Percival Silkstone. He was killed by the environment. That’s why. Now, if you don’t mind, I shall return to my gorgeous, aromatic latte.

Tags: MOSFETs, on resistance

Reliable Reliability

July 20, 2010

  With an IQ of 181, you might think it’s hard for me to amuse myself, but it’s not true. I like a little light reading in the evening…things like Kreck and Lück’s The Novikov Conjecture (A group G is a-T-menable, or, equivalently, has the Haagerup property if G admits a metrically proper isometric action on some affine Hilbert space, page 205) or Carver Mead’s Collective Electrodynamics (Because the system spatial attributes of the system in an eigenstate are stationary, the system in an eigenstate cannot radiate energy, page 106.)

 Fascinating, riveting stuff, I’m sure you agree.

 This led me to think a little bit about semiconductor reliability, though I confess my thinking might have been influenced by the consumption of a bottle of Puligny Montrachet Grand Cru Domaine des Comtes Lafon. In case you’re unfamiliar, that’s a wine very similar in appearance to the Franzia Crisp White wine you can buy in a box at the local market.

 I mentioned Carver Mead above. Among his many accomplishments, he was the guy who contributed to Moore’s Law (which says transistor density on an integrated circuit will approximately double every two years) when Gordon Moore worked at Fairchild Semiconductor in the 1960s.

 In 1965, Gordon had just started making his plots, where he’d plot the logarithm of the number of transistors on a chip as a function of the year. They’re little hand-drawn plots. I still have some around. One day we were talking about his plots. He said “You’re working on electron tunneling that happens when things get really small, right?” Yeah. “Well, wouldn’t that limit how small you can make a transistor?” Yes. “Well, how small is that?” Gordon has a way of asking these very simple questions that you really think you should know the answer to, and I didn’t. I said, well, I have to go and think about it. I’ve been thinking about it ever since. Carver Mead, from a speech at Telecosm 2006

 The driver for Moore’s Law is the fact that as we make transistors smaller, they get cheaper to manufacture AND they work better. Isn’t that something? They work better. Think about that. And, what do we mean by working better? They consume less power and they can switch more quickly. This is the small miracle that fuels the marvelous advances of the digital revolution.

 Today Fairchild is a leader in power management and mobile technology and in our factories, over 50 years after Fairchild Semiconductor was originally formed, we continue to take advantage of the state-of-the-art in transistor lithography.

 There are not many businesses like ours where customers expect continuous improvement in products-with lower prices every year. Generally, if you buy the bargain brand at the big-box discount store, you expect lower quality…fewer features and less reliability. If you buy an inexpensive car, you expect it to be less comfortable and less reliable than a premium brand. But, that’s not how the semiconductor business works. Regardless of what you pay for our product, you expect high reliability…robust and rugged components.

 Year-by-year, we practice continuous improvement and do our part to produce parts with very low failure rates. As a semi-random example, we publish a 3.65 FIT (Failure in Time) rating for the n-channel FET NDT3055. This works out to one failure for 3,127 years of operation.

 Let’s take a closer look at what this means. We can’t build up a significantly significant number of parts and test them for 3,127 years. We’d love to, but we can’t. The FIT rating is based on accelerated testing of sample parts with numbers plugged into a formula.

 The basic idea is that by aging sample devices with high humidity and overvoltage stress, we can estimate the failure rate without waiting for tens of thousands of years.

 As I mentioned above, we do our part to create robust devices for our customers. However, is there also a role for the customer? Of course there is.

 In building up our reliability estimate, we use a temperature stress factor adapted from the Arrhenius equation-which includes this term:

eEa/k(1/Tu - 1/Ts)

Where:

Ea = Semiconductor activation energy

k = Boltzmann’s Constant

Tu = use temperature (K), or the die temperature in the design.

Ts = stress temperature (K) used in the accelerated life test.

 We control the stress temperature and it is based on the semiconductor process, generally either 150 degrees C (423K) or 175 degrees C (448K). You control the use temperature. Lower operating temperatures result in higher reliability. That’s your part of the job.

 So, let’s say you want to increase the reliability of a system. Using the free MTBF tool referenced at the end of this blog, we can see the predicted effect of reducing the operating temperature from 100 degrees C to 90 degrees C.

 At 100C, the calculated FIT is 1009.

At 90C, the calculated FIT is 860.

Is that enough of an improvment? That depends on your needs.

Please note I am not saying anything about the fundamental reality of these numbers. They are numbers, but there is a fair amount of speculation and unconsidered factors in a real life design.

 It’s getting late and I notice there is about a half a glass left in the bottle. I suppose I could put the cork back in and save that last bit for later.

 Or not.

 The unpublished papers referenced below are available by request.

 The author would like to thank Thomas Welch and Raymond Oakley who collectively contributed three unhelpful suggestions and two rude comments during the writing of this article.

 References

On Acceleration Factors used in Failure Rate Prediction - Unpublished paper by Thomas Welch, Director, Quality and Reliability, Fairchild Semiconductor

Secrets of Mean Time Between Failure - Unpublished paper by Raymond Oakley, Staff Customer Quality Engineer, Fairchild Semiconductor

Free MTBF tool from Advanced Logistics Developments, Free MTBF Tool

Failure Mechanisms and Models for Semiconductor Devices, JEDEC Publication, JEP122E

Reliability by Design, A. C. Brombacher, John Wiley and Sons

Reliability, Maintainability and Availability Assessment, Mitchell O. Locks, Hayden Book Company

Collective Electrodynamics, Carver A. Mead, The MIT Press

The Novikov Conjecture, Matthias Kreck and Wolfgang Lück, Birkhauser Verlag

Tags: Dr. FAE, Fairchild Semiconductor, reliability, semiconductors

Would you care for an IC?

May 7, 2010

Instead of answering one of the many technical questions that cross my desk, I hope you’ll indulge me while I digress to tell you about the party I attended in Manhattan last week. Perhaps you saw pictures from this gathering…it was hosted by the widow of a moderately infamous oil mogul and many of the single-name-only crowd were there: Angie and Brad, Jewel, Cher, Sting, Jen, Björk, Moby and others, as were a random collection of B-list partiers…rappers, lobbyists, literary agents, fashion models….and the ever-present John Q. Fields-you know, the ubiquitous actor with the very high IQ (but not quite so high as mine, thank you very much).

The first thing you’ll want to know is how an engineer gets an invitation to a party like this, but I can’t help you. That’s a path you’ll have to blaze on your own.

After a stare-down with the bartender who tried to insult me with an exceptionally average Cognac when, from a prior visit to this expansive apartment, I knew there was a bottle of Cognac Dudognon Héritage HENRI IV hidden in a secret storage nook behind the hallway Matisse print (Woman with a Hat, or rather, an inept counterfeit). I was minding my own business by the fireplace when a pretty TV actress planted the heel of one of her Jimmy Choo slingbacks directly on my instep. After accepting her profuse apology, we struck up a conversation and she asked what I do for a living.

“I work for a semiconductor company…a famous one with a long history of accomplishment and invention.” But it had no meaning or relevance to her. She looked at me as if I was speaking in tongues-until I explained.

“Unless you’re an electrical engineer, you might not be familiar with Fairchild Semiconductor, but it’s highly likely that you own many of our products. For example, do you own a brand name flatscreen TV? Then, most likely, you own numerous Fairchild components. Do you have a game console? The most popular ones are built with Fairchild parts. Do you drive a car with a navigation system? Do you have a cell phone with a digital still camera? Do you have a DVR? A computer? An Energy Star® air conditioner or washing machine? A printer? A music player? We’re everywhere and you are our customer! Your life is probably overflowing with hundreds of our tiny, energy-saving, feature-enhancing components. You might not know our name, but we reduce the energy consumption of your computer, provide the backlighting for your LCD TV, increase the talk time on your cell phone, and generally power your world.”

As you might imagine, she swooned-and peppered me with questions about our support for soon-to-be-released cell phone features and enhancements, which I will share later.

Then, eavesdroppers quickly spread the word. Many stopped by to shake my hand and kiss my cheek…and thank me for our contributions to their way of life…for helping to create and power all the beautiful things that enrich and enable our fabulous modern lifestyle.

Snifters of the secret stash of cognac finally came my way, but I could hardly find a quiet moment to enjoy a sip.

Oh, my friends, celebrity can be such a heavy burden.

But, have no worry.

I can handle it.

I’ll be fine.

Tags: Dr. FAE, energy-saving device, Fairchild Semiconductor, feature-enhancing components

Zero ESR Filter Capacitors — Effect on Feedback Loop Compensation

March 16, 2010

Dear Dr. FAE
I did a good deed and replaced the output filter capacitors in my voltage mode control DC:DC power supply with a zero-ESR (Equivalent Series Resistance) versions. Now my power supply is unstable when the load rapidly changes and my boss is mad. Is it true that no good deed goes unpunished? — Frustrated in Fortuna

Dear Frustrated,
It’s such a simple problem… I’m constantly surprised at how people overcomplicate things. If you’re designing a feedback loop, then negative feedback is your friend-it contributes to stability. Positive feedback contributes to turning your amplifier into an oscillator. The feedback loop uses an inverting amplifier. That’s 180 degrees of phase shift. Unfortunately, there are other factors that add to this 180 degrees and if they contribute too much, it eats into your margin and moves closer to changing your sweet negative feedback into dangerous positive feedback.

Beyond mentioning voltage mode control, you haven’t given me any circuit details, but that does not trouble me. I see nearly all and know almost everything-it’s one of the key advantages of having a very high IQ (181, thank you for asking). You have a buck converter and it has an LC network on the output that looks like this:

Figure 1 - SPICE Simulation

If we pretend the capacitor ESR is zero…it’s a low pass filter and the -3db corner frequency is:

It’s a 2-pole circuit, so the slope of the response above the corner frequency is -40dB/decade. This is illustrated by the SPICE simulation result-note the characteristic resonant “peaking” of the output around the corner frequency (the solid trace) and the very rapid phase change (dotted trace) from zero to 180 degrees. That rapid phase change makes the loop difficult to stabilize. Any signal anywhere near that frequency quickly becomes positive feedback. Oh no!

As a rule-of-thumb, we’d like the slope of the response to be -20dB/decade when it crosses the zero-gain line with a maximum phase lag of 90 degrees (represented by a 1-pole circuit). If only there was a way to change the -40dB/decade response to -20dB/decade. For free. For once, we can use a parasitic element to assist with the desired response…the frequency response zero created by the capacitor ESR.

The corner frequency for the zero created by the RESR and CAP network is located at:

Beyond this corner frequency, the slope of the response changes from -40dB/decade to -20db/decade…that’s the slope we want when the gain crosses zero. Let’s see what adding a reasonable value of ESR (100 mOhm) in series looks like in the frequency range we’re interested in.

Figure 2 - Add Capacitor ESR

Notice: now the phase change is headed toward 90 degrees and not 180 degrees.

It’s great to reduce ESR. After all, the ESR losses represent wasted energy. So, all hail zero ESR capacitors (including ceramic capacitors). However, the power supply loop design must take this into account. Typically, this means adding a capacitor to the Type-2 compensation network to create a Type-3 network. Later, I will be happy to discuss the Type-3 network in infinite detail. Another way to simplify the feedback network is to use a current mode controller (which allows us to visualize the output as a current source and sort of removes the filter inductor from the feedback loop, but that’s another topic for yet another day).

I want to make sure to address all of your questions, even the off-topic philosophical ones.

So, is it true that no good deed goes unpunished? Yes, indeed. Sad, but true.

References:
Abe Pressman’s Switching Power Supply Design (Second Edition) McGraw-Hill
Optimum Feedback Amplifier Design for Control Systems, Timothy E. Biesecker (http://www.venable.biz/tp-03.pdf)

Tags: buck converter, DC:DC power supply, feedback loop, Zero ESR Filter Capacitors

What’s Up with Feedback Loops?

October 23, 2009

Dear Mister Baffled,

If we’re talking about making people’s lives easier, you could connect our parts to well-behaved loads with well-behaved sources and we could sell you expensive resistors in fancy packages and make a lot of money.

However, most parts that provide a regulated output have a feedback loop for control and enhanced stability. Sometimes this feedback loop is buried inside the part…in that case we design a control loop we think will work well for a variety of circuits a customer might hook it to. Even a simple device like a Low-Dropout (LDO) regulator has a feedback loop from the output to control the conduction of the pass transistor. This is why, in rare situations, when a load is ill-behaved or a board layout is poor or bypass capacitors are improperly selected-the output will oscillate. In a feedback loop, we’re always trying to balance the aggressiveness of the response (the speed that the regulator will respond to load changes) with stability over temperature, component variation, worst case circuit and device influences. This brings up subjects like Bode plots and phase/gain margin that are uncomfortable for some people.

So, when you look at designing with a part like the FAN21SV04 and see the external feedback loop components, we’re trying to do you a service. You can adjust the feedback compensation to meet the transient requirements of your design.  So I hope you agree - including a feedback loop will make your life easier.

Now if you’ll excuse me, I have to visit my therapist.

Tags: Dr. FAE, external feedback loop, FAN21SV04, feedback loop, LDO

Dr. FAE: Voltage Feed-Forward Feature for Power Supply Controllers

September 21, 2009

Dear Dr. Fred A. Engleberry. Could you please explain the advantage of the voltage feed-forward feature of many of your power supply controllers? - -      Puzzled in Peoria

Greetings to you in Peoria.

My IQ is 181 so, certainly, I could explain the advantage of voltage feed-forward. In anticipation of your next question, I will elaborate…

This morning, over a warm, half-caf, double-short, non-fat latté at the local coffee shop, I was enjoying a recreational review of Kreck and Lück’s Novikov Conjecture (Geometry and Algebra) which says the following:

Finally, we indicate the proof of Theorem 16.2 for arbitrary n. The idea is to work inductively. If f is a diffeomorphism on Tⁿ X P with P a 1-connected manifold, one can isotope it so that it preserves N^n-1 X P.

My thinking might be illustrated more clearly with a transfer function from Erickson and Maksimovich, Fundamentals of Power Electronics:

This formula clearly shows that input voltage is not a variable. It contains a built-in assumption that the input voltage is invariant. Adding input voltage greatly complicates the transfer function.

Dear Doctor FAE, pardon me, but I do not recognize that answer as plain English.

-         PiP

Very well, I shall explain without the crystal clarity of the simple equation. The control loop of a DC-DC converter operates by sampling the output voltage and adjusting the pulse width modulation of the power train. The control loop acts as follows: if the output voltage changes, then we adjust power supply to counteract the change and keep the output stable.

However, if the input voltage changes, the power supply must respond to this change too. We could wait for the effect of the input change to appear at the power supply output, but wouldn’t it be glorious if we could monitor the input voltage and adjust the PWM immediately without waiting for the output voltage to change…if we provided some direct control method that did not complicate the feedback loop?

That’s the advantage of voltage feed-forward.

We do this by allowing the input voltage to directly modulate the slope of the PWM ramp. With an increased input voltage, the slope of the ramp increases and crosses the feedback signal sooner, giving a shorter output control pulse. Get it? Thus, increasing Vin reduces the PWM control signal outside of the output voltage control loop.

Now, if you’ll excuse me… I’ll be seeking a refreshing nap.

Tags: DC-DC converter, power supply controllers, voltage feed-forward

Why did my FET fail?

August 25, 2009

We’re introducing a new blogger to the site: Dr. Fred A. Engleberry. Dr. F.A.E. holds a PhD from MIT (Muckton Institute of Talknology) and has several months of valuable experience with applied technology. We are pleased to have Dr. F.A.E. available to answer questions collected from customers around the world.

Dr. F.A.E, “Smoky” from General Specifics Inc. sent a question…”Why did my FET fail?” Without further ado, we’ll turn the session over to Dr. Fred.

First of all, Smoky, you’re probably expecting a lot of annoying questions about your design. Such as, what frequency you’re running at, what the gate drive circuit looks like, what the load is and what supply voltage is present. Some design engineers might try to determine whether there is an avalanche condition beyond what the device might be reasonably expected to tolerate, whether the gate drive is insufficient or oscillating, whether the load is inductive, whether voltage spikes creep too close to breakdown voltages on the gate or drain, or whether the total package dissipation is being exceeded.

However, let’s say in this instance I could see your schematic and Bill of Materials (BOM). Your gate resistor, R42, as noted on the schematic, should be one ohm, but the BOM shows 1,000 ohms. Replace this resistor with the proper value and you will find that your FET turn-on and turn-off rise and fall times will become reasonable and you will avoid gate oscillation – and your FET design will become robust.

Want more information on FETs? Check out our website for MOSFETs at http://fairchildsemi.com/products/mosfets/index.html

Tags: Dr. FAE, FET designs, FET failed, gate oscillation, MOSFETs