Archive for the ‘Dr. Efficiency’ Category

Getting More Efficiency with Synchronous Rectification MOSFETs

Tuesday, January 26th, 2010
Dear Dr. Efficiency, I used a synchronous rectifier MOSFET with large current and low RDSON in a forward converter structure for synchronous rectification (SR) and expected there would be a significant improvement in efficiency.  However nothing happened.  Why was that?  I thought that the SR MOSFET should make a significant contribution to efficiency improvement.  - XM Wang

Hello XM,
You are on the right track, but may need to make some corrections. To deal with the power loss, we have to consider two aspects.

The power loss of semiconductor switches mainly comes from two sources: the conduction loss resulting from the loss on the RDSON that is generated when ID goes through the body diode during dead time, and the switching loss which can be roughly classified as three components: the loss caused from current-voltage cross when the MOSFET switches between turn-on and cut-off, the loss on the parasitic capacitance during switching, and that caused by the trr time of the body diode in the MOSFET.

 sr-mosfet-blog

 

 

 

 

The above equations show the close relation between the switching loss and the switching frequency. In particular, the loss during dead time mainly depends on the switching frequency, since the dead time is usually fixed. In general, for a given output power, the higher the frequency the more switching loss portion dominance; the lower the frequency the more conduction loss portion dominance.

In a SR structure, the body diode is already turned on by freewheel current before the MOSFET turns on. Since the voltage drop on the body diode is usually less than 2V, the conduction loss is not significant in equation (1).

Equation (2) shows the effect on the switching caused by the parasitic capacitance (Coss) of the MOSFET. This Coss is the equivalent capacitance between drain and source, with a voltage equal to Vds applied. Thus, this portion of loss is proportional to the switching frequency and Vds. You can check if the loss in your design is mainly caused by Coss by paralleling a smaller capacitance between the drain and the source to make the two MOSFETs have almost the same Coss value, then analyze the results by using the equations given above. You’ll get an idea about why the efficiency improvement is not significant.

Finally, in a forward half-bridge structure, the switching loss contributed by trr is also significant since the secondary current is usually kept in continuous current mode. You can check if the loss in your design is caused by trr by paralleling a schottky diode on the SR MOSFET side and then observing whether the efficiency is improved notably. If the efficiency is improved significantly, you can select a MOSFET with shorter trr time for the SR MOSFET.

Now, go back to your question. For MOSFETs within the same series, the lower the RDSON, the larger the value of parasitic capacitance. For example, FDP047N10 from Fairchild Semiconductor has a RDSON of 4.7mohm and a Coss of 1500pF, whereas FDP100N10 has a RDSON of 10mohm, but its Coss is only 710pF. In other words, it is possible that the lower RDSON FDP047N10 may have a larger loss under high switching frequency due to its larger Coss. Other parameters, such as Qg, parasitic body diode in MOSFET, also contribute to the overall power loss, which compromises the efficiency improvement effect of lower Rds. So, apart from the RDSON, which should be as low are also possible, the parasitic characteristic is an important factor in MOSFET selection.

Hope you are satisfied with my explanation. Let’s go and have a cup of coffee.

Author Information: DR. Efficiency

Peak current mode PWM and slope compensation

Friday, January 8th, 2010

Dr. Efficiency,

Why does my power supply’s output suffer duty cycle fluctuation? I’m experiencing one big duty cycle followed by a small duty cycle. The pulses with large duty cycles almost occupy the maximum T(on) time and only those with small duty cycles can be modulated. My power supply uses a UC3842 PWM controller. Both the feed and the input voltage are smooth. Can poor PCB layout introduce interference? What are the disadvantages of this issue? How do I solve the problem?

 - Mr. Zhang

Mr. Zhang,

According to your circuit architecture, the UC3842 PWM controller used in your power supply works in Peak-Current Mode (PCM) and I think you may be experiencing sub-harmonic oscillation.

The PCM PWM controller has superior load regulation characteristics and anti-input interference capability, which makes it easy to implement current-limiting and over-current protection. It is stable in feedback and easy to compensate, hence widely used.

However, PCM PWM has a unique feature: when in continuous conduction mode (CCM) and with a duty cycle over 0.5, the angle between the rising curve of the inductor current and control voltage are smaller than that between the falling curve and the control voltage.  And in this case, we assume that there is a small disturbance occurring in the initial inductor current in one cycle. Then at the end of this cycle or at the beginning of the next cycle, the disturbance will be amplified and after several cycles of disturbance accumulation, duty cycle fluctuation will become one big duty cycle followed by a small duty cycle, or so-called sub-harmonic oscillation will occur.

This is an inherent feature of any open loop system which uses PCM PWM. It has nothing to do with the feedback or the PCB layout. Here we also understand that even with D<0.5, sub-harmonic oscillation could also be induced, depending on the angle between the rising curve of the inductor current and control voltage and the angle between the falling curve and the control voltage.

Sub-harmonic oscillation can make open-loop systems unstable, more susceptible to interference and in serious cases, it can even reduce the switch frequency by half and decrease the output power. This problem can be solved by making the duty cycle <0.5, or by compensating the current slopes. Slope compensation can be implemented by adding a signal with a fixed slope on the detected current signal or by adding a reverse slope signal on the control voltage to increase the angle between the current slope and the control voltage. With these measures taken, the possibility of sub-harmonic oscillation will decrease and the useable range of duty cycle will be widened.

 However, it should be noted that if the current slope is over-compensated, the advantage of PCM PWM will be off-set. To be specific, the higher the compensation, the more the PWM behaves like a voltage mode PWM. So it is important to have a proper slope compensation design. To facilitate the design procedure, Fairchild has integrated the slope compensation function within its newly introduced FAN6754 and FAN6753 PCM PWM ICs, providing you with more flexibility and a larger duty cycle range during design. In addition, the device also limits the maximum duty cycle, reducing the impact of sub-harmonic oscillation on the system and freeing you from undesirable compensation tasks.

 I hope you are satisfied with my explanation. Let’s go and have a cup of coffee.

Author Information: DR. Efficiency

What should we do to achieve high efficiency and power in LED street lamps ?

Monday, December 21st, 2009

The power requirement of LED street lamps being used in China falls in the range of 100~250W. It is widely agreed that if used properly, these kinds of LED street lamps deliver many advantages. What I want to explain here is the ways to make it possible for these lamps to deliver those advantages. The key factors to be considered are high efficiency, power, reliability and cost-effectiveness.

Some low-power lighting requires PFC, while high-power lamps usually require PFC combined with DC/DC requirements. In China where the AC line voltage is 220V, Boundary-Conduction Mode (BCM) PFC controllers, such as the FAN7530 and the FAN6961, become the ideal choice to maintain a balance between the efficiency and performance-cost ratio. These solutions only need a few components.

Low Rds(on) SupreMOS(TM) MOSFETs, can further decrease switch and conduction loss. When used at the boost output, the HyperFAST 2 high voltage diode family with lower Vf can also lower the conduction loss of the diode itself.

For DC/DC topology, there are many choices such as quasi-resonant (QR), double transistor forward (DTF), active-clamp, LLC and asymmetrical half-bridge (AHB). High-power lighting applications, for example in a 100W lamp, where the output voltage is usually a little high, QR working with a synchronous rectifier can achieve up to 92.5% of total efficiency. Moreover, Fairchild has integrated QR and BCM PFC into one package (the FAN6921), reducing external components and simplifying the control.

Another popular topology is zero voltage switch (ZVS). Both an LLC and an AHB can have their two bridges working in zero voltage by implementing a simple circuit. When using Fairchild’s highly-integrated solution (for example, a LLC controller and two MOSFETs in FSFR; an AHB controller and two MOSFETs in FSFA2100), the circuit can be further simplified, with few external components. And the body diode of the MOSFET has good fast recovery characteristic, which can reduce the possibility of short-through, yet provide high reliability with high efficiency. When the output voltage is high, an LLC is the better option; when the output voltage is low, an AHB is more suitable for implementing a self-driven synchronous rectifier, and both can achieve over 93~94% efficiency.

The above solutions are highly integrated solutions and require just a few components, thus delivering high efficiency, high power density, optimized thermal performance as well as high reliability.

Click here for more information on LED lighting from Fairchild.

Author Information: DR. Efficiency