Dr. Efficiency,

Why does my power supply’s output suffer duty cycle fluctuation? I’m experiencing one big duty cycle followed by a small duty cycle. The pulses with large duty cycles almost occupy the maximum T(on) time and only those with small duty cycles can be modulated. My power supply uses a UC3842 PWM controller. Both the feed and the input voltage are smooth. Can poor PCB layout introduce interference? What are the disadvantages of this issue? How do I solve the problem?

 - Mr. Zhang

Mr. Zhang,

According to your circuit architecture, the UC3842 PWM controller used in your power supply works in Peak-Current Mode (PCM) and I think you may be experiencing sub-harmonic oscillation.

The PCM PWM controller has superior load regulation characteristics and anti-input interference capability, which makes it easy to implement current-limiting and over-current protection. It is stable in feedback and easy to compensate, hence widely used.

However, PCM PWM has a unique feature: when in continuous conduction mode (CCM) and with a duty cycle over 0.5, the angle between the rising curve of the inductor current and control voltage are smaller than that between the falling curve and the control voltage.  And in this case, we assume that there is a small disturbance occurring in the initial inductor current in one cycle. Then at the end of this cycle or at the beginning of the next cycle, the disturbance will be amplified and after several cycles of disturbance accumulation, duty cycle fluctuation will become one big duty cycle followed by a small duty cycle, or so-called sub-harmonic oscillation will occur.

This is an inherent feature of any open loop system which uses PCM PWM. It has nothing to do with the feedback or the PCB layout. Here we also understand that even with D<0.5, sub-harmonic oscillation could also be induced, depending on the angle between the rising curve of the inductor current and control voltage and the angle between the falling curve and the control voltage.

Sub-harmonic oscillation can make open-loop systems unstable, more susceptible to interference and in serious cases, it can even reduce the switch frequency by half and decrease the output power. This problem can be solved by making the duty cycle <0.5, or by compensating the current slopes. Slope compensation can be implemented by adding a signal with a fixed slope on the detected current signal or by adding a reverse slope signal on the control voltage to increase the angle between the current slope and the control voltage. With these measures taken, the possibility of sub-harmonic oscillation will decrease and the useable range of duty cycle will be widened.

 However, it should be noted that if the current slope is over-compensated, the advantage of PCM PWM will be off-set. To be specific, the higher the compensation, the more the PWM behaves like a voltage mode PWM. So it is important to have a proper slope compensation design. To facilitate the design procedure, Fairchild has integrated the slope compensation function within its newly introduced FAN6754 and FAN6753 PCM PWM ICs, providing you with more flexibility and a larger duty cycle range during design. In addition, the device also limits the maximum duty cycle, reducing the impact of sub-harmonic oscillation on the system and freeing you from undesirable compensation tasks.

 I hope you are satisfied with my explanation. Let’s go and have a cup of coffee.