By Guy Moxey, Low Voltage Power, Product Marketing

With the emergence of important climate saving legislation such as 80 PLUS, Climate Savers and EnergyStar® 5, analog designers for DC-DC power systems are striving to meet the challenge of increasing system level efficiency across all operating power states. From this, power silicon products such as power IC’s and power MOSFET’s are now very much in vogue as these devices create and dissipate the vast majority of any low voltage power conversion in-circuit losses that, in turn, directly relate to the system’s overall efficiency.

Take a typical notebook, typical peak efficiencies for a 46A, 2 phase Notebook VCORE solution with PWM controller and discrete MOSFET implementation are typically @90% peak at current ratings of 10A per phase, reducing down to @86% at full loads of 23A. This 10-13% loss in system efficiency is directly proportional to power and thermal dissipation. The complete notebook system is normally @ 50-60W output and running at 85% efficiency so that translates to a 9W power waste for every note book PC in the form of heat and battery life.

At start up or during a heavy processing sequence, the power system is dominated by conduction losses ( I2R) of the low side MOSFET. Here select a ultra high cell density low RDS(ON) FET housed in a dual sided cooled package so that the losses will be significantly minimized. However, as most PC s spend a majority of their operating life in standby or sleep states, it’s essential that the power system allows for light load efficiency management where gate drive and switching losses are predominant at low output currents below 10A. Here driver impedance and MOSFETs have to be carefully optimized. Gate drive voltages of 5V are preferred with MOSFETs with ultra low gate charge. The driver IC can pulse skip switching cycles to minimize MOSFET switching loss and also low-drive disable to effectively blank out the low side MOSFET completely allow for discontinuous conduction mode operation.

By careful MOSFET selection, close optimization with the driver IC, the design can start to move toward a higher level of overall system efficiency. Full load thermal design points can inch upward toward the 90% level, medium to light load levels can be touching 95% and ultra light loads don’t immediately take a dive southward with such velocity. But while we progress and save a few watts of loss over today’s designs, there is still some significant silicon research and development to be done before the utopian power curve can be seen.

All too often during product design, well intentioned product managers, rightfully scared from prior EMI encounters, especially during the beginning of a new project, schedule large amounts of time for EMI evaluation and prevention. Program managers add in time for the illusively fiendish problems that always seem to delay projects at the very end. As schedules inevitably are delayed, the big gaps are minimized to small gaps, or eliminated. The simulations and Printed Circuit Board (PCB) evaluations and trace routing guidelines are placed in the hands of the PCB Autorouter.

Often, the EMI engineer at the end of a project will carry the new consumer product back from his/her EMI chamber and trusty spectrum analyzer, with a fist full of graphs with large peaks and valleys. “It’s got problems”, he/she says, “but we can fix it. You just need to eliminate this spike from the system clock that is generating harmonics large enough to turn on a light bulb.” Rerouting the clock requires a new Printed Circuit Board layout. That can, in itself, create new problems associated with parasitics. The next PCB revision takes a full eight weeks to design, populate, test and evaluate.

This time, the clock traces have been placed too close to the image sensor system. The result is that when the camera is turned on with this new handset, the video screen has vertical bars from left to right corrupting the screen. Again, the device is put through EMI testing. This time the handset passes with flying colors…. however, due to the close proximity of the image sensor system, the PCB must be redesigned yet again. What has been your experience in solving these challenges?