What do you mean - more power, less heat?

October 27, 2010

As the trends for greater efficiency and power consumption increase, the concern for heat transfer increases as well. Designers have already taken the necessary steps to improve heat transfer at rails requiring higher power such as at the CPU and GPU, by incorporating various thermal dissipation methods. But what about the DC/DC power supplies? Power engineers are finding that certain areas of the printed circuit board become too hot, and in certain instances, they’ve had to redesign the buck regulator or resort to heat sink usage on the MOSFETs as a last minute fix.

This is where Dual Cool^TM packaging comes into play. With today’s top-side cooled packaging technology, the form factor and pad design is different than what engineers are used to seeing. However, there is no issue with familiarity when it comes to Dual Cool packaging versus PQFN because the Dual Cool package is simply a thermal performance upgrade to PQFN. It allows for additional top-side cooling. With enhanced dual path thermal performance and improved parasitics over its wire-bonded predecessors, the use of a heat sink with the Dual Cool package provides even more impressive results.

A heat sinked Dual Cool package allows synchronous buck converters to deliver higher output current, which increases power density. These packages are green, lead-free, RoHS-compliant and available in 3×3 and 5×6 QFN packages.

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Tags: Dual Cool, efficiency, Energy Efficiency, packaging, power consumption

Power management solutions improve operating time in mobile handsets

July 26, 2010

Written by Wayne Seto, Technical Marketing Manager

With the proliferation of cellular mobile handsets, especially smartphones, in the world today where people are connected 24/7, consumers just can’t seem to get enough of the voice calls, emails, text messages and surfing the web. However, all of these activities greatly consume battery life in our handsets; as such, our handhelds lead to that one-bar battery power indicator very quickly. In this article from the June 1, 2010 edition of EDN Asia, Wayne Seto discusses what can be done to prolong the battery life for these handsets so that we can use them longer.

Read the complete article

Tags: efficiency, Energy Efficiency, Fairchild Semiconductor, power management

Getting More Efficiency with Synchronous Rectification MOSFETs

January 26, 2010

Dear Dr. Efficiency, I used a synchronous rectifier MOSFET with large current and low RDSON in a forward converter structure for synchronous rectification (SR) and expected there would be a significant improvement in efficiency.  However nothing happened.  Why was that?  I thought that the SR MOSFET should make a significant contribution to efficiency improvement.  - XM Wang
Hello XM,
You are on the right track, but may need to make some corrections. To deal with the power loss, we have to consider two aspects.

The power loss of semiconductor switches mainly comes from two sources: the conduction loss resulting from the loss on the RDSON that is generated when ID goes through the body diode during dead time, and the switching loss which can be roughly classified as three components: the loss caused from current-voltage cross when the MOSFET switches between turn-on and cut-off, the loss on the parasitic capacitance during switching, and that caused by the trr time of the body diode in the MOSFET.

The above equations show the close relation between the switching loss and the switching frequency. In particular, the loss during dead time mainly depends on the switching frequency, since the dead time is usually fixed. In general, for a given output power, the higher the frequency the more switching loss portion dominance; the lower the frequency the more conduction loss portion dominance.

In a SR structure, the body diode is already turned on by freewheel current before the MOSFET turns on. Since the voltage drop on the body diode is usually less than 2V, the conduction loss is not significant in equation (1).

Equation (2) shows the effect on the switching caused by the parasitic capacitance (Coss) of the MOSFET. This Coss is the equivalent capacitance between drain and source, with a voltage equal to Vds applied. Thus, this portion of loss is proportional to the switching frequency and Vds. You can check if the loss in your design is mainly caused by Coss by paralleling a smaller capacitance between the drain and the source to make the two MOSFETs have almost the same Coss value, then analyze the results by using the equations given above. You’ll get an idea about why the efficiency improvement is not significant.

Finally, in a forward half-bridge structure, the switching loss contributed by trr is also significant since the secondary current is usually kept in continuous current mode. You can check if the loss in your design is caused by trr by paralleling a schottky diode on the SR MOSFET side and then observing whether the efficiency is improved notably. If the efficiency is improved significantly, you can select a MOSFET with shorter trr time for the SR MOSFET.

Now, go back to your question. For MOSFETs within the same series, the lower the RDSON, the larger the value of parasitic capacitance. For example, FDP047N10 from Fairchild Semiconductor has a RDSON of 4.7mohm and a Coss of 1500pF, whereas FDP100N10 has a RDSON of 10mohm, but its Coss is only 710pF. In other words, it is possible that the lower RDSON FDP047N10 may have a larger loss under high switching frequency due to its larger Coss. Other parameters, such as Qg, parasitic body diode in MOSFET, also contribute to the overall power loss, which compromises the efficiency improvement effect of lower Rds. So, apart from the RDSON, which should be as low are also possible, the parasitic characteristic is an important factor in MOSFET selection.

Hope you are satisfied with my explanation. Let’s go and have a cup of coffee.

Tags: conduction loss, efficiency, MOSFET, power loss, semiconductor switches, switching loss, synchronous rectifier